NETSOL S7N803631M
The S7N803631M and S7N801831M are 9,437,184-bits Synchronous Static SRAMs. The NTSRAM, or Non-Turnaround Static Random Access Memory utilizes all the bandwidth in any combination of operating cycles. The S7N803631M and S7N801831M are implemented with high performance CMOS technology and is available in 100pin TQFP package.| Part No. | S7N803631M |
|---|---|
| Datasheet | S7N803631M Download |
| Manufacturer | NETSOL |
| Description | 256Kx36 & 512Kx18 NTSRAM Sync-Pipelined Burst |
| Buy | Stock & Price |
FEATURES
● Fully registered inputs and outputs for pipelined operation● VDD = 2.5V(2.3V ~ 2.7V) or 3.3V(3.1V ~ 3.5V) Power Supply
● VDDQ= 2.3V~2.7V I/O Power Supply (VDD=2.5V) or 2.3V~3.5V I/O Power Supply (VDD=3.3V)
● Byte Writable Function
● Enable clock and suspend operation
● Single Read/Write control pin
● Asynchronous output enable control
● Self-timed Write control
● Three Chip Enable for simple depth expansion with no data contention
● An interleaved burst or a linear burst mode
● Power Down mode
● Operating in commeical and industrial temperature range
● 100-TQFP-1420A (Lead free package)
GENERAL DESCRIPTION
Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals.
