S7Q161862M Description
The S7Q163662M and S7Q161862M are 18,874,368-bits Quadruple Synchronous Pipelined Burst SRAMs. The Quadruple operation is possible by supporting DDR read and write operations through separate data output and input.
S7Q161862M Key Features
- 1.8V/2.5V +0.1V/-0.1V Power Supply
- I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O
- HSTL I/O
- Full data coherency, providing most current data
- Synchronous pipeline read with self timed early write
- Registered address, control and data input/output
- DDR (Double Data Rate) Interface on read and write ports
- Fixed 2-bit burst for both read and write operation
- Clock-stop supports to reduce current. -Two input clocks (K and K) for accurate DDR timing at clock
- Separate read/write control pin (R and W)