NETSOL S7S3218U2M
The S7S3236U2M and S7S3218U2M are 37,748,736-bits Quadruple Synchronous Pipelined Burst SRAMs. They are organized as 1,048,576 words by 36bits for S7S3236U2M, 2,097,152 words by 18bits for S7S3218U2M. The Quadruple operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle.| Part No. | S7S3218U2M |
|---|---|
| Datasheet | S7S3218U2M Download |
| Manufacturer | NETSOL |
| Description | 1Mx36 & 2Mx18 Quadruple-II+ BL2 SRAM |
| Buy | Stock & Price |
FEATURES
KEY PARAMETERS
● 1.8V+0.1V/-0.1V Power Supply.● DLL circuitry for wide output data valid window and future fre- quency scaling.
● I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O.
● Separate independent read and write data ports with concurrent read and write operation Part Number Org. Freq. (MHz) S7S3236U2M-E(F)C(I)45 450 S7S3236U2M-E(F)C(I)40 x36 400 Cycle Access Time Time RoHS (ns) (ns) 2.2 0.45 Ο 2.5 0.45 Ο
● HSTL I/O
● Full data coherency, providing most current data.
● Synchronous pipeline read with self timed early write. S7S3236U2M-E(F)C(I)36 S7S3218U2M-E(F)C(I)45 366 2.7 0.45 Ο 450 2.2 0.45 Ο
● Read latency : 2.5 clock cycles S7S3218U2M-E(F)C(I)40 x18 400 2.5 0.45 Ο
● Registered address, control and data input/output.
● DDR (Double Data Rate) Interface on read and write ports. S7S3218U2M-E(F)C(I)36 366 2.7 0.45 Ο
● Fixed 2-bit burst for both read and write operation.
● Clock-stop supports to reduce current.
● Two input clocks (K and K) for accurate DDR timing at clock rising edges only.
