NETSOL S7S6418U2M
The S7S6436U2M and S7S6418U2M are 75,497,472-bits Quadruple Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for S7S6436U2M, 4,194,304 words by 18bits for S7S6418U2M. The Quadruple operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle.| Part No. | S7S6418U2M |
|---|---|
| Datasheet | S7S6418U2M Download |
| Manufacturer | NETSOL |
| Description | 2Mx36 & 4Mx18 Quadruple-II+ BL2 SRAM |
| Buy | Stock & Price |
FEATURES
KEY PARAMETERS
● 1.8V+0.1V/-0.1V Power Supply.● DLL circuitry for wide output data valid window and future fre- quency scaling.
● I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O. Part Number Org. Freq. (MHz) S7S6436U2M-E(F)C(I)45 450 Cycle Access Time Time RoHS (ns) (ns) 2.2 0.45 Ο
● Separate independent read and write data ports with concurrent read and write operation
● HSTL I/O S7S6436U2M-E(F)C(I)40 x36 400 2.5 0.45 Ο S7S6436U2M-E(F)C(I)36 366 2.7 0.45 Ο
● Full data coherency, providing most current data.
● Synchronous pipeline read with self timed early write.
● Read Latency : 2.5 clock cycles S7S6418U2M-E(F)C(I)45 450 2.2 0.45 Ο S7S6418U2M-E(F)C(I)40 x18 400 2.5 0.45 Ο
● Registered address, control and data input/output. S7S6418U2M-E(F)C(I)36 366 2.7 0.45 Ο
● DDR (Double Data Rate) Interface on read and write ports.
● Fixed 2-bit burst for both read and write operation.
● Clock-stop supports to reduce current.
● Two input clocks (K and K) f...
