NETSOL S7S6418U4M
The S7S6436U4M, S7S6418U4M and S7S6409U4M are 75,497,472-bits Quadruple Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for S7S6436U4M, 4,194,304 words by 18bits for S7S6418U4M and 8,388,608 words by 9bits for S7S6409U4M. The Quadruple operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle.| Part No. | S7S6418U4M |
|---|---|
| Datasheet | S7S6418U4M Download |
| Manufacturer | NETSOL |
| Description | 2Mx36 & 4Mx18 & 8Mx9 Quadruple-II+ BL4 SRAM |
| Buy | Stock & Price |
FEATURES
● 1.8V+0.1V/-0.1V Power Supply.● DLL circuitry for wide output data valid window and future fre- quency scaling.
● I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O.
● Separate independent read and write data ports with concurrent read and write operation
● HSTL I/O
● Full data coherency, providing most current data .
● Synchronous pipeline read with self timed late write.
● Read latency: 2.5 clock cycles
● Registered address, control and data input/output.
● DDR(Double Data Rate) Interface on read and write ports.
● Fixed 4-bit burst for both read and write operation.
● Clock-stop supports to reduce current.
● Two input clocks(K and K) for accurate DDR timing at clock rising edges only.
● Two echo clocks (CQ and CQ) to enhance output data traceability.
● Data Valid pin(QVLD) supported
● Single address bus.
● Byte write (x9, x18, x36) function.
● Separate read/write control pin(R and W)
● Simple depth expansion with no data contention.
● Programmable output impedance(ZQ).
