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S7T1618U4M - 512Kx36 & 1Mx18 & 2Mx9 Quadruple-II+ BL4 SRAM w/ ODT

This page provides the datasheet information for the S7T1618U4M, a member of the S7T1636U4M 512Kx36 & 1Mx18 & 2Mx9 Quadruple-II+ BL4 SRAM w/ ODT family.

Datasheet Summary

Description

The S7T1636U4M, S7T1618U4M and S7T1609U4M are 18,874,368-bits Quadruple Synchronous Pipelined Burst SRAMs.

They are organized as 524,288 words by 36bits for S7T1636U4M, 1,048,576 words by 18bits for S7T1618U4M and 2,097,152 words by 9bits for S7T1609U4M.

Features

  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future fre- quency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O.
  • Separate independent read and write data ports with concurrent read and write operation.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed late write.
  • Read latency: 2.5 clock cycle.

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Datasheet preview – S7T1618U4M

Datasheet Details

Part number S7T1618U4M
Manufacturer NETSOL
File Size 401.19 KB
Description 512Kx36 & 1Mx18 & 2Mx9 Quadruple-II+ BL4 SRAM w/ ODT
Datasheet download datasheet S7T1618U4M Datasheet
Additional preview pages of the S7T1618U4M datasheet.
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Full PDF Text Transcription

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SS77TT11663366UU44MM SS77TT11661188UU44MM SS77TT11660099UU44MM 551122KKxx3366&&11MMxx1188&&22MMxx99QQuuaaddrruuppllee--III++BBLL44SSRRAAMMww//OODDTT 18Mb Quadruple-II+ BL4 w/ ODT SRAM Specification (2.5 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of NETSOL.
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