NETSOL S7T4418T2M
The S7T4436T2M, S7T4418T2M and S7T4409T2M are 150,994,944-bits Quadruple Synchronous Pipelined Burst SRAMs. They are organized as 4,194,304 words by 36bits for S7T4436T2M, 8,388,608 words by 18bits for S7T4418T2M and 16,777,216 words by 9bits for S7T4409T2M. The Quadruple operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle.FEATURES
KEY PARAMETERS
● 1.8V+0.1V/-0.1V Power Supply.● DLL circuitry for wide output data valid window and future fre- quency scaling.
● I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ Part Number Org. Freq. (MHz) Cycle Access Time Time RoHS (ns) (ns) -0.1V for 1.8V I/O.
● Separate independent read and write data ports with concurrent read and write operation S7T4436T2M-E(F)C(I)35 X36 357 2.8 0.45 Ο S7T4436T2M-E(F)C(I)33 333 3.0 0.45 Ο
● HSTL I/O
● Full data coherency, providing most current data.
● Synchronous pipeline read with self timed early write.
● Read Latency : 2 clock cycles
● Registered address, control and data input/output.
● DDR (Double Data Rate) Interface on read and write ports. S7T4418T2M-E(F)C(I)35 X18 357 2.8 0.45 Ο S7T4418T2M-E(F)C(I)33 333 3.0 0.45 Ο S7T4409T2M-E(F)C(I)35 X9 357 2.8 0.45 Ο S7T4409T2M-E(F)C(I)33 333 3.0 0.45 Ο
● Fixed 2-bit burst for both read and write operation.
● Clock-stop supports to reduce current.
● Two input clocks (K and K)...