NETSOL S7T6409T2M
The S7T6436T2M, S7T6418T2M and S7T6409T2M are 75,497,472-bits Quadruple Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for S7T6436T2M, 4,194,304 words by 18bits for S7T6418T2M and 8,388,608 words by 9bits for S7T6409T2M. The Quadruple operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle.| Part No. | S7T6409T2M |
|---|---|
| Datasheet | S7T6409T2M Download |
| Manufacturer | NETSOL |
| Description | 2Mx36 & 4Mx18 & 8Mx9 Quadruple-II+ BL2 SRAM w/ ODT |
| Buy | Stock & Price |
FEATURES
KEY PARAMETERS
● 1.8V+0.1V/-0.1V Power Supply.● DLL circuitry for wide output data valid window and future fre- quency scaling.
● I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ Part Number Org. Freq. (MHz) Cycle Access Time Time RoHS (ns) (ns) -0.1V for 1.8V I/O.
● Separate independent read and write data ports with concurrent read and write operation
● HSTL I/O S7T6436T2M-E(F)C(I)40 400 2.5 0.45 Ο S7T6436T2M-E(F)C(I)35 X36 357 2.8 0.45 Ο S7T6436T2M-E(F)C(I)33 333 3.0 0.45 Ο
● Full data coherency, providing most current data.
● Synchronous pipeline read with self timed early write.
● Read Latency : 2 clock cycles S7T6436T2M-E(F)C(I)30 S7T6418T2M-E(F)C(I)40 300 3.3 0.45 Ο 400 2.5 0.45 Ο
● Registered address, control and data input/output.
● DDR (Double Data Rate) Interface on read and write ports.
● Fixed 2-bit burst for both read and write operation. S7T6418T2M-E(F)C(I)35 X18 357 2.8 0.45 Ο S7T6418T2M-E(F)C(I)33 333 3.0 0.45 Ο
● Clock-stop supports to reduce current.
