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74LVC2G241 - Dual buffer/line driver

General Description

The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs.

A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state.

A LOW level at pin 2OE causes output 2Y to a

Key Features

  • I I I I Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Mu.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LVC2G241 Dual buffer/line driver; 3-state Rev. 07 — 5 October 2007 www.DataSheet4U.com Product data sheet 1. General description The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE: • A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. • A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF.