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ADC1004S040 - Single 10-bits ADC

Download the ADC1004S040 datasheet PDF. This datasheet also covers the ADC1004S030 variant, as both devices belong to the same single 10-bits adc family and are provided as variant models within a single manufacturer datasheet.

General Description

The ADC1004S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital Converters (ADC) for professional video and other applications.

They convert the analog input signal into 10-bit binary-coded digital signals at a maximum sampling rate of 50 MHz.

Key Features

  • I I I I I I I I I I I I I I 10-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (9.4 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) No missing codes guaranteed In-Range (IR) CMOS output TTL and CMOS levels compatible digital inputs 3 V to 5 V CMOS digital outputs Low-level AC clock input signal allowed External reference voltage regulator Power dissipation only 175 mW.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADC1004S030_NXPSemiconductors.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by NXP Semiconductors

Part Number Description
ADC1004S030 Single 10-bits ADC
ADC1004S050 Single 10-bits ADC
ADC1002S020 Single 10 bits ADC
ADC1003S030 Single 10-bits ADC
ADC1003S040 Single 10-bits ADC

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ADC1004S030/040/050 Rev. 03 — 7 August 2008 www.DataSheet4U.com Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz Product data sheet 1. General description The ADC1004S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital Converters (ADC) for professional video and other applications. They convert the analog input signal into 10-bit binary-coded digital signals at a maximum sampling rate of 50 MHz. All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible, although a low-level sine wave clock input signal is allowed. The device requires an external source to drive its reference ladder.