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LPC2124 - Single-chip 16/32-bit microcontrollers

Download the LPC2124 datasheet PDF. This datasheet also covers the LPC2114 variant, as both devices belong to the same single-chip 16/32-bit microcontrollers family and are provided as variant models within a single manufacturer datasheet.

General Description

The LPC2114/2124 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 128/256 kB of embedded high-speed flash memory.

A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate.

Key Features

  • 2.1 Key features brought by LPC2114/2124/01 devices.
  • Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device. They also allow for a port pin to be read at any time regardless of its function.
  • Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are 5 V tolerant when configured for digital I/O function(s).
  • UART0/1 include fractional baud rate generator, auto-bauding capabilities and handshake flow-control fully implemented.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (LPC2114_NXPSemiconductors.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
LPC2114/2124 Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP flash with 10-bit ADC Rev. 7 — 10 June 2011 Product data sheet 1. General description The LPC2114/2124 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 128/256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.