Datasheet Details
| Part number | UDA1352TS |
|---|---|
| Manufacturer | NXP Semiconductors |
| File Size | 303.72 KB |
| Description | 48 kHz IEC 60958 audio DAC |
| Datasheet | UDA1352TS_NXPSemiconductors.pdf |
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Overview: INTEGRATED CIRCUITS DATA SHEET UDA1352TS 48 kHz IEC 60958 audio DAC Preliminary specification Supersedes data of 2002 May 22 2002 Nov 22 NXP Semiconductors 48 kHz IEC 60958 audio DAC CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.2 9.3 9.4 9.5 9.6 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.
| Part number | UDA1352TS |
|---|---|
| Manufacturer | NXP Semiconductors |
| File Size | 303.72 KB |
| Description | 48 kHz IEC 60958 audio DAC |
| Datasheet | UDA1352TS_NXPSemiconductors.pdf |
|
|
|
ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Clock regeneration and lock detection Mute Auto mute Data path Control L3-BUS DESCRIPTION General Device addressing Register addressing Data write mode Data read mode Initialization string I2C-BUS DESCRIPTION Characteristics of the I2C-bus Bit transfer Byte transfer Data transfer Start and stop conditions Acknowledgment Device address Register address Write and read data Write cycle Read cycle Preliminary specification UDA1352TS 11 11.1 11.2 11.3 11.4 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 19.5 20 21 22 SPDIF SIGNAL FORMAT SPDIF channel encoding SPDIF hierarchical layers for audio data SPDIF hierarchical layers for digital data Timing characteristics REGISTER MAPPING SPDIF mute setting (write) Power-down settings (write) Volume control left and right (write) Sound
| Part Number | Description |
|---|---|
| UDA1352HL | 48 kHz IEC 60958 audio DAC |
| UDA1350AH | IEC 958 audio DAC |
| UDA1350ATS | IEC 958 audio DAC |
| UDA1351H | 96 kHz IEC 958 audio DAC |
| UDA1351TS | 96 kHz IEC 958 audio DAC |
| UDA1355H | Stereo audio codec |