4014BT Datasheet | NXP Semiconductors

HEF4014B 8-bit static shift register Rev. 9 - 21 March 2016 Product data sheet 1. General description The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (D0 to D7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW-to-HIGH edge-triggered clock input (CP) and buffered parallel outputs from the last three stages (Q5 to Q7). Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH transition of CP. Each register stage is of a D-type master-slave flip-flop type. When PE is HIGH, data is loaded into the register from D0 to D7 on the LOW-to-HIGH transition of CP. When PE...