4042B Datasheet | NXP Semiconductors

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered plementary latch outputs (O0 to O3) and two mon enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the same state, either HIGH or LOW. O0 to O3 follow D0 to D3 as long as both E0 and E1 remain in the same state. When E0 and E1 are different, D0 to D3 do not affect O0 to O3 and the information in the latch is stored. O0 to O3 are always the plement of O0 to O3. The exclusive-OR input structure allows the choice of either polarity for E0 and E1. With one enable input HIGH, the other enable input is active HIGH; with one enable input LOW, the other enable input is active LOW. HEF4042B MSI Fig.2 Pinning diagram. HEF4042BP(N): HEF4042BD(F): HEF4042BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING D0 to D3 E0 and E1 O0 to O3 O0 to O3 data inputs enable inputs parallel latch outputs plementary parallel latch outputs APPLICATION INFORMATION Some examples of applications for the HEF4042B are: - Buffer storage - Holding register FAMILY DATA, IDD LIMITS category MSI See Family Specifications Fig.1 Functional diagram. January 1995 Philips Semiconductors Product specification Quadruple D-latch FUNCTION TABLE E0 L L H H Note E1 L H L H HEF4042B MSI OUTPUT On Dn latched latched Dn 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage). Fig.3 Logic diagram. Fig.4 Logic diagram (one latch). January 1995 Philips Semiconductors Product specification Quadruple D-latch AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 p F; input transition times ≤ 20 ns VDD V Propagation delays D → O, O HIGH to LOW 5 10 15 5 LOW to HIGH E → O, O HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH Set-up time D→E Hold...