DESCRIPTION
HEF4071B gates Fig.2 Pinning diagram. HEF4071BP(N): 14-lead DIL; plastic (SOT27-1) HEF4071BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4071BT(D): 14-lead SO; plastic Fig.1 Functional diagram. (SOT108-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category GATES See Family Specifications Fig.3 Logic diagram (one gfate). January 1995 2 Philips Semiconductors Product specification Quadruple 2-input OR gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL 55 25 20 45 20 15 60 30 20 60 30 20 115 50 35 90 45 30 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns 28 ns 15 ns 12 ns 18 ns 9 ns 7 ns 10 ns 9 ns 6 ns 10 ns 9 ns 6 ns + + + + + + + + + + + + SYMBOL TYP. MAX. HEF4071B gates TYPICAL EXTRAPOLATION FORMULA (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55...
NXP Semiconductors
