Description
The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths
Features
- Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops.
- Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors.
- Live insertion/extraction permitted.
- Power-up 3-State.
- Power-up Reset.
- Output capability: +64 mA/.
- 32 mA.
- Latch-up protection exceeds 500 mA per Jedec Std 17.
- ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per M.
74ABT16823A Datasheet
