74ABT273A Overview
The 74ABT273A has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The mon buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered.
74ABT273A Key Features
- Eight edge-triggered D-type flip-flops
- Buffered mon clock
- Buffered asynchronous Master Reset
- Power-up reset
- See 74ABT377 for clock enable version
- See 74ABT373 for transparent latch version
- See 74ABT374 for 3-State version
- ESD protection exceeds 2000 V per Mil Std 833 Method 3015 and
