NXP Semiconductors 74AHCT02
The 74AHC/AHCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. The 74AHC/AHCT02 provides the Quad 2-input OR function.| Part No. | 74AHCT02 |
|---|---|
| Datasheet | 74AHCT02 Download |
| Manufacturer |  NXP Semiconductors |
| Description | Quad 2-input NOR gate |
| Buy | Stock & Price |
FEATURES
● ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V● Balanced propagation delays
● All inputs have Schmitt-trigger actions
● Inputs accepts voltages higher than VCC
● For AHC only: operates with CMOS input levels
● For AHCT only: operates with TTL input levels
● Specified from −40 to +85 and +125 °C.
DESCRIPTION
7A. FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. nB L H L H OUTPUT nY H L L L QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. 74AHC02; 74AHCT02 TYPICAL SYMBOL tPHL/tPLH CI CO CPD PARAMETER propagation delay nA, nB to nY input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V 2.9 AHCT 3.8 3.0 4.0 8.0 ns pF pF pF UNIT VI = VCC or GND 3.0 4.0 7.0 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (...
