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74AHCT132 - Quad 2-input NAND Schmitt trigger

General Description

The 74AHC/AHCT132 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard No.

7A.

Key Features

  • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V; MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V.
  • Balanced propagation delays.
  • Inputs accepts voltages higher than VCC.
  • For AHC only: operates with CMOS input levels.
  • For AHCT only: operates with TTL input levels.
  • Specified from.
  • 40 to +85 and +125 °C.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS DATA SHEET 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Product specification Supersedes data of 1999 May 31 File under Integrated Circuits, IC06 1999 Sep 24 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V; MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • Inputs accepts voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 and +125 °C. DESCRIPTION The 74AHC/AHCT132 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.