Download 74AHCT257 Datasheet PDF
74AHCT257 page 2
Page 2
74AHCT257 page 3
Page 3

74AHCT257 Description

The 74AHC/AHCT257 are high-speed Si-gate CMOS devices and are pin patible with Low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard No. The 74AHC/AHCT257 has four identical 2-input multiplexers with 3-state outputs, which select 4 bits of QUICK REFERENCE DATA GND = 0.

74AHCT257 Key Features

  • Balanced propagation delays
  • All inputs have Schmitt-trigger actions
  • Non-inverting data path
  • Inputs accept voltages higher than VCC
  • For AHC only: operates with CMOS input levels
  • For AHCT only: operates with TTL input levels