74ALS273 Description
The 74ALS273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The mon buffered clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The register is fully edge-triggered.
74ALS273 Key Features
- Eight edge-triggered D-type flip-flops
- Buffered mon clock
- Buffered asynchronous master reset
- See 74ALS377 for clock enable version
- See 74ALS373 for transparent latch version
- See 74ALS374 for 3-State version