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74ALS377 - Octal D flip-flop

General Description

The 74ALS377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.

The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is Low.

The register is fully edge-triggered.

Key Features

  • Ideal for addressable register.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS 74ALS377 Octal D flip–flop with enable Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Philips Semiconductors Product specification Octal D flip-flop with enable 74ALS377 FEATURES • Ideal for addressable register applications • Enable for address and data synchronization applications • Eight edge-triggered D-type flip-flops • Buffered common clock • See 74ALS273 for master reset version • See 74ALS373 for transparent latch version • See 74ALS374 for 3-State version DESCRIPTION The 74ALS377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is Low. The register is fully edge-triggered.