74ALS648-1 Overview
Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes High. Output enable (OE) and direction (DIR) and select (SAB, SBA) pins are provided for bus management. One (1.0) ALS unit load is defined as:.
74ALS648-1 Key Features
- Independent registers for A and B buses
- Multiplexed real-time and stored data
- Choice of non-inverting and inverting data paths
- 3-State outputs
- The -1 version sink 48mA IOL within the ±5% VCC range
- B7 CPAB CPBA SAB SBA DIR OE A0
- A7, B0
- A7, B0