NXP Semiconductors 74ALVC574
The 74ALVC574 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition.| Part No. | 74ALVC574 |
|---|---|
| Datasheet | 74ALVC574 Download |
| Manufacturer |  NXP Semiconductors |
| Description | Octal D-type flip-flop |
| Buy | Stock & Price |
FEATURES
● Wide supply voltage range from 1.65 to 3.6 V● Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).
● 3.6 V tolerant inputs/outputs
● CMOS low power consumption
● Direct interface with TTL levels (2.7 to 3.6 V)
● Power-down mode
● Latch-up performance exceeds ≤250 mA
● ESD protection: 2000 V Human Body Model (JESD22-A114-A) 200 V Machine Model (JESD22-A115-A).
DESCRIPTION
74ALVC574 A clock (CP) input and an output enable (OE) input are common to all flip-flops. When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The ‘574’ is functionally identical to the ‘374’, but the ‘374’ has a different pin arrangement. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay CP to Qn CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ VCC = 2...
