Description
output enable input (active LOW) 3-state flip-flop output ground (0 V) clock input (LOW-to-HIGH, edge triggered) data input supply voltage 2002 Mar 04 3 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74ALVC574 handbook, halfpage OE 1 D0 2 D1 3 D2 4 D3 5 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 handbook, halfpage 11 2 3 4 5 6 7 8 9 CP D0 D1 D2 D3 D4 D5 D6 D7 OE 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 574 D4 6 D5 7 D6 8 D7 9 GND 10 MNA444 15 Q4 14 Q5 13 Q6 12 Q7 11 CP MNA445 Fig.1 Fig.2 Logic symbol. handbook, halfpage 11 1 C1 EN handbook, halfpage 2 3 19 18 17 16 15 14 13 12 MNA446 D0 D1 D2 D3 D4 D5 D6 D7 FF1 to FF8 3-STATE OUTPUTS Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 2 3 4 5 6 7 8 9 1D 4 5 6 7 8 9 11 CP 1 OE MNA447 Fig.3 IEE/IEC logic symbol.
Key Features
- Wide supply voltage range from 1.65 to 3.6 V
- 3.6 V tolerant inputs/outputs
- CMOS low power consumption
- Direct interface with TTL levels (2.7 to 3.6 V)
- Power-down mode
- Latch-up performance exceeds ≤250 mA
