74ALVCH162601 Overview
74ALVCH162601 The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting 3-state bus patible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.
74ALVCH162601 Key Features
- plies with JEDEC standard no. 8-1A
- CMOS low power consumption
- Direct interface with TTL levels
- MULTIBYTE™ flow-through standard pin-out architecture
- Low inductance multiple VCC and ground pins for minimum noise and ground bounce
- All data inputs have bus hold circuitry
- Integrated 30 Ω termination resistors. DESCRIPTION
