74ALVCH16952 Description
The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bi-directional busses. Data applied to the inputs is entered and stored on the rising edge of the clock (CPXX, where X is AB or BA) provided that the clock enable (CEXX) is LOW.
74ALVCH16952 Key Features
- plies with JEDEC standard no. 8-1A
- CMOS low power consumption
- MULTIBYTETM flow-through pin-out architecture
- Direct interface with TTL levels
- Output drive capability 50Ω transmission lines @ 85°C