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74ALVT16899 - 2.5V/3.3V 18-bit latched transceiver

General Description

The 74ALVT16899 has three principal modes of operation which are outlined below.

All modes apply to both the A-to-B and B-to-A directions.

Key Features

  • Symmetrical (A and B bus functions are identical).
  • Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input. The 74ALVT16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.
  • Independent trans.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS 74ALVT16899 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) Product specification IC23 Data Handbook 1998 Jun 30 Philips Semiconductors Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 FEATURES • Symmetrical (A and B bus functions are identical) • Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input.