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74AUP1G126 - Low-Power buffer/line driver

General Description

The 74AUP1G126 provides a single non-inverting buffer/line driver with 3-state output.

The 3-state output is controlled by the output enable input (OE).

A LOW level at pin OE causes the output to assume a high-impedance OFF-state.

Key Features

  • Wide supply voltage range from 0.8 V to 3.6 V.
  • High noise immunity.
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3 V).
  • JESD8-11 (0.9 V to 1.65 V).
  • JESD8-7 (1.2 V to 1.95 V).
  • JESD8-5 (1.8 V to 2.7 V).
  • JESD8-B (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114F Class 3A exceeds 5000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101E exceeds 1000 V.
  • Low static power consump.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74AUP1G126 Low-power buffer/line driver; 3-state Rev. 9 — 14 January 2022 Product data sheet 1. General description The 74AUP1G126 provides a single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A LOW level at pin OE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input OE is LOW. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.