74AUP1G240 Datasheet | NXP Semiconductors

description The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS patible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature , which allows floating input signals. The inputs are disabled when the output enable input OE is HIGH. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s plies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-D exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 m A per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s Input-disable feature allows floating input conditions NXP Semiconductors Low-power inverting buffer/line driver; 3-state s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from - 40 °C to +85 °C and - 40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1G240GW 74AUP1G240GM 74AUP1G240GF - 40 °C to +125 °C - 40 °C to...