74AUP1G240 - Low-power inverting buffer/line driver

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NXP

Part number	74AUP1G240
Manufacturer	NXP
File Size	125.27 KB
Description	Low-power inverting buffer/line driver
Datasheet	74AUP1G240 Datasheet
Additional preview pages of the 74AUP1G240 datasheet.

The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-D exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltage.

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Published: Jan 19, 2007 |