74AUP1G885 Datasheet PDF (Low Power Dual Function Gate)

74AUP1G885 - Low Power Dual Function Gate

Description

The 74AUP1G885 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Features

s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114D Class 3A exceeds 4000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept.

Datasheet Details

Part number	74AUP1G885
Manufacturer	NXP
File Size	133.98 KB
Description	Low Power Dual Function Gate
Datasheet	74AUP1G885 Datasheet
Additional preview pages of the 74AUP1G885 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com 74AUP1G885 Low-power dual function gate Rev. 01 — 1 December 2006 Product data sheet 1. General description The 74AUP1G885 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully speciﬁed for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backﬂow current through the device when it is powered down. The 74AUP1G885 provides two functions in one device.

Published: Mar 2, 2007 |