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74AUP1G885 Datasheet PDF

NXP Semiconductors 74AUP1G885

The 74AUP1G885 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF.
Part No. 74AUP1G885
Datasheet 74AUP1G885 Download
Manufacturer
NXP Semiconductors
Description Low Power Dual Function Gate
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74AUP1G885 datasheet page 1 preview

FEATURES

s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114D Class 3A exceeds 4000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C NXP Semiconductors 74AUP1G885 Low-power dual function gate 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1G885DC 74AUP1G885GT 74AUP1G885GM −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C VSSOP8 XSON8 XQFN8

DESCRIPTION

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