74F112 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS 74F112 Dual J-K negative edge-triggered flip-flop Product specification IC15 Data Handbook 1990 Feb 09 Philips Semiconductors Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop FEATURE - Industrial temperature range available (- 40°C to +85°C) DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and plementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs...