NXP Semiconductors 74F112
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs. The logic levels at the J and K inputs may be allowed to change while the CPn is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed.
| Part No. |
74F112 |
| Datasheet |
74F112
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| Manufacturer |
 NXP Semiconductors |
| Description |
Dual J-K negative edge-triggered flip-flop |
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DESCRIPTION
A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. Output changes are initiated by the High-to-Low transition of the CPn. TYPE 74F112 TYPICAL PROPAGATION DELAY 100MHz PIN CONFIGURATION CP0 K0 J0 SD0 Q0 Q0 Q1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RD0 RD1 CP1 K1 J1 SD1 Q1 SF00103 TYPICAL SUPPLY CURRENT (TOTAL) 15mA ORDERING INFORMATION ORDER CODE DESCRIPTION
16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F112N N74F112D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C I74F112N I74F112D PKG DWG # SOT38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS J0, J1 K0, K1 SD0, SD1 RD0, RD1 CP0, CP1 Q0, Q0; Q1, Q1 J inputs K inputs Set inputs (active Low) Reset inputs (active Low) Clock Pulse input (active falling edge) Data outputs DESCRIPTION
74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/5.0 1.0/5.0 1.0/4.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/3.0mA 20µA/3.0mA 20µA/2.4mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
