74F132 Datasheet | NXP Semiconductors

DESCRIPTION The 74F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have greater noise margin than conventional NAND gates. Each circuit contains a 2-input Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem-pole output. The Scmitt trigger uses positive feedback to effectively speed-up slow input transitions and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input threshold (typically 800m V) is determined by resistor ratios and is essentially insensitive to temperature and supply voltage variations. As long as three inputs remain at a more positive voltage than VT+MAX, the gate will respond in the transition of the other input as shown in Waveform 1. PIN CONFIGURATION D0a D0b Q0 D1a D1b Q1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC D3b D3a Q3 D2b D2a Q2 SF00710 TYPE TYPICAL PROPAGATION DELAY 6.3ns TYPICAL SUPPLY CURRENT (TOTAL) 13m A ORDERING INFORMATION DESCRIPTION 14-pin plastic DIP 14-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F132N N74F132D PKG DWG # SOT27-1 SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS Dna, Dnb Qn DESCRIPTION Data inputs Data output 74F (U.L.) HIGH/LOW 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6m A 1.0m A/20m A NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL & 2 4 D0a D0b D1a D1b D2a D2b D3a D3b 5...