74F138 Datasheet | NXP Semiconductors

FEATURE - Demultiplexing capability - Multiple input enable for easy expansion - Ideal for memory chip select decoding - Industrial temperature range available (- 40°C to +85°C) DESCRIPTION The 74F138 decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled, provides eight mutually exclusive, active low outputs (Q0 - Q7). The device features three enable inputs; two active low (E0, E1) and one active high (E2). Every output will be high unless E0 and E1 are low and E2 is high. This multiple enable function allows easy parallel expansion of the device to 1-of-32 (5 lines to 32 lines) decoder with just four 74F138s and one inverter (see Figure 1). The device can be used as an eight output demultiplexer by using one of the active low enable inputs as the data input and the remaining enable inputs as strobes. Enable inputs not used must be permanently tied to their appropriate active high or active low state. PIN CONFIGURATION A0 A1 A2 E0 E1 E2 Q7 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 SF00174 TYPE 74F138 TYPICAL PROPAGATION DELAY 5.8ns TYPICAL SUPPLY CURRENT (TOTAL) 13m A ORDERING INFORMATION ORDER CODE DESCRIPTION 16-pin plastic DIP 16-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F138N N74F138D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = - 40°C to +85°C I74F138N I74F138D PKG DWG # SOT38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A0 - A2 E0, E1 E2 Q0 - Q7 Address inputs Enable inputs (active Low) Enable input (active High) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 1.0m A/20m A NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the Low state. LOGIC SYMBOL 1 2 3 IEC/IEEE SYMBOL DMUX 0 2 G A0 A1 A2 3 2 0 3 0 1 2 3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 4 5 15 14 13 12 11 10 9 7 6 4 14 13 12 11 4 5 6 E0 E1 E2 & 5 6 7 10 9 7 VCC = Pin 16 GND = Pin 8 SF00175 SF00176 February...