DESCRIPTION
Every output will be high unless E0 and E1 are low and E2 is high. This multiple enable function allows easy parallel expansion of the device to 1-of-32 (5 lines to 32 lines) decoder with just four 74F138s and one inverter (see Figure 1). Enable inputs not used must be permanently tied to their appropriate active high or active low state. PIN CONFIGURATION A0 A1 A2 E0 E1 E2 Q7 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 SF00174 TYPE 74F138 TYPICAL PROPAGATION DELAY 5.8ns TYPICAL SUPPLY CURRENT (TOTAL) 13mA ORDERING INFORMATION ORDER CODE DESCRIPTION
16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F138N N74F138D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C I74F138N I74F138D PKG DWG # SOT38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A0 – A2 E0, E1 E2 Q0 – Q7 Address inputs Enable inputs (active Low) Enable input (active High) Data outputs DESCRIPTION
74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.
NXP Semiconductors
