NXP Semiconductors 74F154
The 74F154 decoder accepts four active High binary address inputs and provides 16 mutually exclusive active Low outputs. The 2-input Enable (E0, E1) gate can be used to strobe the decoder to eliminate the normal decoding “glitches” on the outputs, or it can be used for expansion of the decoder. The enable gate has two AND’ed inputs which must be Low to enable the outputs.FEATURES
● 16-line demultiplexing capability● Mutually exclusive outputs
● 2-input enable gate for strobing or expansion
DESCRIPTION
The 74F154 can be used as 1-of-16 demultiplexer by using one of the Enable inputs as the multiplexed data input. When the other Enable is Low, the addressed output will follow the state of the applied data. TYPICAL PROPAGATION DELAY 5.5 ns TYPICAL SUPPLY CURRENT (TOTAL) 26mA ORDERING INFORMATIONDESCRIPTION
24-pin plastic Slim DIP (300mil) 24-pin plastic SOL COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F154N N74F154D PKG DWG # SOT222-1 SOT137-1 PIN CONFIGURATION Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1 2 3 4 5 6 7 8 9 10 11 24 23 22 21 20 19 18 17 16 15 14 13 VCC A0 A1 A2 A3 E0 E1 Q15 Q14 Q13 Q12 Q11 TYPE 74F154 Q8 Q9 Q10 GND 12 SF00681 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A0 – A3 E0, E1 Q0 – Q15 Data inputs Enable inputs Data outputsDESCRIPTION
74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.