NXP Semiconductors 74F163A
the 74F163A, the clear function is synchronous. This action occurs regardless of the levels at PE, CET, and CEP inputs. The carry look-ahead simplifies serial cascading of the counters.FEATURES
● Synchronous counting and loading● Two count enable inputs for n-bit cascading
● Positive edge-triggered clock
● Asynchronous Master Reset (74F161A)
● Synchronous Reset (74F163A)
● High speed synchronous expansion
● Typical count rate of 130MHz
● Industrial range (–40°C to +85°C) available
DESCRIPTION
4-bit binary counters feature an internal carry look-ahead and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the Parallel Enable (PE) input disables the counting action and causes the data at the D0–D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at Count Enable (CEP, CET) inputs. A Low level at the Master Reset (MR) input...