74F175A
FEATURES
- Four edge-triggered D-type flip-flops
- Buffered mon clock
- Buffered asynchronous Master Reset
- True and plementary outputs
- Industrial temperature range available (- 40°C to +85°C)
- PNP light loading inputs
DESCRIPTION
The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The mon buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. All Q outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where both true and plementary outputs are required, and the CP and MR are mon to all storage elements.
PIN CONFIGURATION
MR 1 16 VCC 15 Q3 14 Q3 13 D3 12 D2 11 Q2 10 Q2 9 CP
Q0 2 Q0 3 D0 4 D1 5 Q1 6 Q1 7 GND...
