NXP Semiconductors 74HC03
The 74HC/HCT03 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. The 74HC/HCT03 have open-drain N-transistor outputs, which are not clamped by a diode connected to VCC.| Part No. | 74HC03 |
|---|---|
| Datasheet | 74HC03 Download |
| Manufacturer |  NXP Semiconductors |
| Description | Quad 2-input NAND gate |
| Buy | Stock & Price |
FEATURES
● Level shift capability● Output capability: standard (open drain)
● ICC category: SSI
GENERAL DESCRIPTION
7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT03 The 74HC/HCT03 provide the 2-input NAND function. In the OFF-state, i.e. when one input is LOW, the output may be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, these devices must have a pull-up resistor to establish a logic HIGH level. TYPICAL SYMBOL tPZL/ tPLZ CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2× fi + ∑ (CL × VCC2 × fo) + ∑ (VO2/RL) × duty factor LOW, where: fi = input frequency in MHz fo = output frequency in MHz VO = output voltage in V CL = output load capacitance in pF VCC = supply voltage in V RL = pull-up resistor in MΩ ∑ (CL × VCC2 × fo) = sum of outputs ∑ (VO2/RL) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V 3.
