74HC4094 Datasheet PDF - NXP 8-stage shift-and-store bus register Specs

74HC4094 - 8-stage shift-and-store bus register

Datasheet Summary

Description

The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Features

Complies with JEDEC standard JESD7A.
Input levels:.
For 74HC4094: CMOS level.
For 74HCT4094: TTL level.
Low-power dissipation.
ESD protection:.
HBM JESD22-A114F exceeds 2 000 V.
MM JESD22-A115-A exceeds 200 V.
Specified from 40 C to +85 C and from 40 C to +125 C 3.

Datasheet Details

Part number	74HC4094
Manufacturer	NXP
File Size	169.50 KB
Description	8-stage shift-and-store bus register
Datasheet	74HC4094 Datasheet
Additional preview pages of the 74HC4094 datasheet.

📁 Similar Datasheet

74HC4094 - 8-bit SIPO shift latch register (STMicroelectronics)

74HC4094 - 8-stage shift-and-store bus register (nexperia)

74HC4094-Q100 - 8-stage shift-and-store bus register (nexperia)

74HC4094D - 8-stage shift-and-store bus register (nexperia)

74HC4094DB - 8-stage shift-and-store bus register (nexperia)

74HC4094PW - 8-stage shift-and-store bus register (nexperia)

74HC4094Y - 8-bit SIPO shift latch register (STMicroelectronics)

74HC4002 - Dual 4-input NOR gate (nexperia)

74HC4002-Q100 - Dual 4-input NOR gate (nexperia)

74HC4002D - Dual 4-input NOR gate (nexperia)

Full PDF Text Transcription

Click to expand full text

74HC4094; 74HCT4094 8-stage shift-and-store bus register Rev. 7 — 10 February 2016 Product data sheet 1. General description The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow.

Published: Jun 1, 2016 |