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74HCT164 - 8-bit serial-in / parallel-out shift register

Download the 74HCT164 datasheet PDF. This datasheet also covers the 74HC164 variant, as both devices belong to the same 8-bit serial-in / parallel-out shift register family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC164; 74HCT164 is an 8-bit serial-in/parallel-out shift register.

Key Features

  • Input levels:.
  • For 74HC164: CMOS level.
  • For 74HCT164: TTL level.
  • Gated serial data inputs.
  • Asynchronous master reset.
  • Complies with JEDEC standard no. 7A.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Multiple package options.
  • Specified from 40 C to +85 C and 40 C to +125 C. NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register 3. Ordering information Table 1. Orderi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC164-NXP.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by NXP Semiconductors

Part Number Description
74HCT165 8-bit parallel-in/serial out shift register
74HCT11 Triple 3-input AND gate
74HCT123 Dual retriggerable monostable multivibrator
74HCT123-Q100 Dual retriggerable monostable multivibrator
74HCT125 Quad buffer/line driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Rev. 7 — 13 June 2013 Product data sheet 1. General description The 74HC164; 74HCT164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.