74HCT4020 Overview
74HCT4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP.
74HCT4020 Key Features
- Wide supply voltage range from 2.0 V to 6.0 V
- Input levels
- For 74HC4020: CMOS level
- For 74HCT4020: TTL level
- Multiple package options
- plies with JEDEC standard no. 7A
- Specified from 40 C to +85 C and from 40 C to +125 C
