NXP Semiconductors 74HCT4518
The 74HC/HCT4518 are high-speed Si-gate CMOS devices and are pin compatible with the “4518” of the “4000B” series. They are specified in compliance with JEDEC standard no. The 74HC/HCT4518 are dual 4-bit internally synchronous BCD counters with an active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs from 74HC/HCT4518 all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous master reset input (nMR).| Part No. | 74HCT4518 |
|---|---|
| Datasheet | 74HCT4518 Download |
| Manufacturer |  NXP Semiconductors |
| Description | Dual synchronous BCD counter |
| Buy | Stock & Price |
FEATURES
● Output capability: standard● ICC category: MSI
GENERAL DESCRIPTION
7A. The counter advances on either the LOW-to-HIGH transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1.APPLICATIONS
● Multistage synchronous counting● Multistage asynchronous counting
● Frequency dividers QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER tPHL/ tPLH tPHL fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = G...
