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74HCT4520-Q100 - Dual 4-bit synchronous binary counter

Download the 74HCT4520-Q100 datasheet PDF. This datasheet also covers the 74HC4520-Q100 variant, as both devices belong to the same dual 4-bit synchronous binary counter family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1).

They have buffered outputs from all 4 bit positions (nQ0 to nQ3), and an asynchronous master reset input (nMR).

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Note: The manufacturer provides a single datasheet file (74HC4520-Q100-NXP.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter Rev. 1 — 4 December 2014 Product data sheet 1. General description The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3), and an asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes.