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74LVC1G07 - Buffer

General Description

The 74LVC1G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

The input can be driven from either 3.3 or 5 V devices.

This feature allows the use of this device as translator in a mixed 3.3 and 5 V environment.

Key Features

  • Wide supply voltage range from 1.65 to 5.5 V.
  • High noise immunity.
  • Complies with JEDEC standard:.
  • JESD8-7 (1.65 to 1.95 V).
  • JESD8-5 (2.3 to 2.7 V).
  • JESD8B/JESD36 (2.7 to 3.6 V).
  • 24 mA output drive (VCC = 3.0 V).
  • CMOS low power consumption.
  • Latch-up performance ≤250 mA.
  • Direct interface with TTL levels.
  • Inputs accept voltages up to 5 V.
  • SOT353 package. QUICK.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS DATA SHEET 74LVC1G07 Buffer with open-drain output Product specification Supersedes data of 2000 Nov 22 File under Integrated Circuits, IC24 2001 Apr 06 Philips Semiconductors Product specification Buffer with open-drain output FEATURES • Wide supply voltage range from 1.65 to 5.5 V • High noise immunity • Complies with JEDEC standard: – JESD8-7 (1.65 to 1.95 V) – JESD8-5 (2.3 to 2.7 V) – JESD8B/JESD36 (2.7 to 3.6 V). • 24 mA output drive (VCC = 3.0 V) • CMOS low power consumption • Latch-up performance ≤250 mA • Direct interface with TTL levels • Inputs accept voltages up to 5 V • SOT353 package. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPLZ/tPZL CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW).