74LVC1G07
Overview
- Wide supply voltage range from 1.65 to 5.5 V
- High noise immunity
- Complies with JEDEC standard: - JESD8-7 (1.65 to 1.95 V) - JESD8-5 (2.3 to 2.7 V) - JESD8B/JESD36 (2.7 to 3.6 V).
- 24 mA output drive (VCC = 3.0 V)
- CMOS low power consumption
- Latch-up performance ≤250 mA
- Direct interface with TTL levels
- Inputs accept voltages up to 5 V
- SOT353 package. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPLZ/tPZL CI CPD Notes
- CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts.
