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74LVC1G126 - Bus buffer/line driver

General Description

The 74LVC1G126 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

The input can be driven from either 3.3 V or 5 V devices.

This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Key Features

  • Wide supply voltage range from 1.65 V to 5.5 V.
  • High noise immunity.
  • Complies with JEDEC standard:.
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8B/JESD36 (2.7 V to 3.6 V).
  • ±24 mA output drive (VCC = 3.0 V).
  • CMOS low power consumption.
  • Latch-up performance exceeds 250 mA.
  • Direct interface with TTL levels.
  • Inputs accept voltages up to 5 V.
  • Multiple package options.
  • E.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS DATA SHEET 74LVC1G126 Bus buffer/line driver; 3-state Product specification Supersedes data of 2002 Oct 02 2004 Sep 21 Philips Semiconductors Product specification Bus buffer/line driver; 3-state FEATURES • Wide supply voltage range from 1.65 V to 5.5 V • High noise immunity • Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V). • ±24 mA output drive (VCC = 3.0 V) • CMOS low power consumption • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Inputs accept voltages up to 5 V • Multiple package options • ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 °C to +85 °C and −40 °C to +125 °C.