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74LVC2G125-Q100 - Dual bus buffer/line driver

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NXP

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74LVC2G125-Q100 Dual bus buffer/line driver by NXP - Datasheet Preview — Datasheet preview – 74LVC2G125-Q100

Datasheet Details

Part number	74LVC2G125-Q100
Manufacturer	NXP
File Size	112.37 KB
Description	Dual bus buffer/line driver
Datasheet	74LVC2G125-Q100 Datasheet
Additional preview pages of the 74LVC2G125-Q100 datasheet.

Product details

Description

The 74LVC2G125-Q100 provides a dual non-inverting buffer/line driver with 3-state output.

The output enable input (pin nOE) controls the 3-state output.

A HIGH-level at pin nOE causes the output to assume a high-impedance OFF-state.

Features

Automotive product qualification in accordance with AEC-Q100 (Grade 1).
Specified from 40 C to +85 C and from 40 C to +125 C.
Wide supply voltage range from 1.65 V to 5.5 V.
5 V tolerant input/output for interfacing with 5 V logic.
High noise immunity.
Complies with JEDEC standard:.
JESD8-7 (1.65 V to 1.95 V).
JESD8-5 (2.3 V to 2.7 V).
JESD8-B/JESD36 (2.7 V to 3.6 V).
ESD protection:.
MIL-STD-883, method 3015 exceeds 2000 V.
HBM.

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Published: Sep 29, 2016 |