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74LVC2G126 - Dual bus buffer/line driver

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NXP

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74LVC2G126 Dual bus buffer/line driver by NXP - Datasheet Preview — Datasheet preview – 74LVC2G126

Datasheet Details

Part number	74LVC2G126
Manufacturer	NXP
File Size	172.50 KB
Description	Dual bus buffer/line driver
Datasheet	74LVC2G126 Datasheet
Additional preview pages of the 74LVC2G126 datasheet.

Product details

Description

The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs.

Each 3-state output is controlled by an output enable input (pin nOE).

A LOW-level at pin nOE causes the output to assume a high-impedance OFF-state.

Features

Wide supply voltage range from 1.65 V to 5.5 V.
5 V tolerant input/output for interfacing with 5 V logic.
High noise immunity.
Complies with JEDEC standard:.
JESD8-7 (1.65 V to 1.95 V).
JESD8-5 (2.3 V to 2.7 V).
JESD8-B/JESD36 (2.7 V to 3.6 V).
ESD protection:.
HBM JESD22-A114F exceeds 2000 V.
MM JESD22-A115-A exceeds 200 V.
24 mA output drive (VCC = 3.0 V).
CMOS low power consumption.
Latch-up performance exceeds 250 mA.
Di.

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Published: Mar 22, 2005 |