NXP Semiconductors 74LVC2G14
The 74LVC2G14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. This feature allows the use of this device as translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff.| Part No. | 74LVC2G14 |
|---|---|
| Datasheet | 74LVC2G14 Download |
| Manufacturer |  NXP Semiconductors |
| Description | Dual inverting Schmitt-trigger |
| Buy | Stock & Price |
FEATURES
● Wide supply voltage range from 1.65 V to 5.5 V● 5 V tolerant input/output for interfacing with 5 V logic
● High noise immunity
● Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V).
● ±24 mA output drive (VCC = 3.0 V)
● CMOS low power consumption
● Latch-up performance exceeds 250 mA
● Direct interface with TTL levels
● Mulltiple package options
● ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V.
● Specified from −40 °C to +85 °C and −40 °C to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C SYMBOL tPHL/tPLH PARAMETER propagation delay input nA to output nY CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ VCC = 2.5 V; CL = 30 pF; RL = 500 Ω VCC = 2.7 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; CL = 50 pF; RL = 500 Ω VCC = 5.0 V; CL = 50 pF; RL = 500 Ω CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VC...
