74LVC827A Datasheet | NXP Semiconductors

FEATURES - 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic - Supply voltage range of 2.7V to 3.6V - plies with JEDEC standard no. 8-1A - CMOS low power consumption - Direct interface with TTL levels - High impedance when VCC = 0V DESCRIPTION The 74LVC827A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS patible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC827A is a10-bit buffer/line driver with 3-State outputs The 3-State outputs are controlled by the output enable inputs OE1 and OE2. A HIGH on OEn causes the outputs to assume a high impedance OFF-state. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL t PHL/t PLH CI CPD PARAMETER Propagation delay An to Yn Input capacitance Power dissipation capacitance per buffer Notes 1 and 2 CONDITIONS CL = 50 p F; VCC = 3.3 V TYPICAL 4 5.0 24 UNIT ns p F p F NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi )ȍ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in p F; fo = output frequency in MHz; VCC = supply voltage in V; ȍ (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES 24-Pin Plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE - 40°C to +85°C - 40°C to +85°C - 40°C to +85°C OUTSIDE NORTH AMERICA 74LVC827A D 74LVC827A DB 74LVC827A PW NORTH AMERICA 74LVC827A D 74LVC827A DB 7LVC827APW DH PKG. DWG. # SOT137-1 SOT340-1 SOT355-1 PIN DESCRIPTION PIN NUMBER 1, 13 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 12 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 24 SYMBOL OE1, OE2 A0 to A9 GND Y0 to Y9 VCC NAME AND FUNCTION Output enable input (active LOW) Data inputs Ground (0 V) Bus outputs Positive supply voltage FUNCTION TABLE INPUTS OE1 L...