80C851 Datasheet | NXP Semiconductors

DESCRIPTION The Philips 80C851/83C851 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The 80C851/83C851 has the same instruction set as the 80C51. The Philips CMOS technology bines the high speed and density characteristics of HMOS with the low power attributes of CMOS. The Philips epitaxial substrate minimizes latch-up sensitivity. The 80C851/83C851 contains a 4k × 8 ROM with mask-programmable ROM code protection, a 128 × 8 RAM, 256 × 8 EEPROM, 32 I/O lines, two 16-bit counter/timers, a seven-source, five vector, two-priority level nested interrupt structure, a serial I/O port for either multi-processor munications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the 80C851/83C851 has two software selectable modes of power reduction - idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM and EEPROM contents but freezes the oscillator, causing all other chip functions to be inoperative. FEATURES - 80C51 based architecture - 4k × 8 ROM - 128 × 8 RAM - Two 16-bit counter/timers - Full duplex serial channel - Boolean processor - Non-volatile 256 × 8-bit EEPROM (electrically erasable programmable read only memory) - On-chip voltage multiplier for erase/write - 10,000 erase/write cycles per byte - 10 years non-volatile data retention - Infinite number of read cycles - User selectable security mode - Block erase capability - Mask-programmable ROM code protection - Memory addressing capability - 64k ROM and 64k RAM - Power control modes: - Idle mode - Power-down mode - CMOS and TTL patible - 1.2 to 16MHz or 3.5 to 24MHz - Three package styles - Three temperature ranges - ROM code protection ORDERING INFORMATION PHILIPS PART ORDER NUMBER PART MARKING ROMless Version P80C851 FBP P80C851 IBP P80C851 FBA P80C851 IBA P80C851 FBB P80C851 IBB P80C851 FFP...