FEATURES AND BENEFITS
SNR, 66.5 dBFS; SFDR, 86 dBc Sample rate: 125 Msps Clock input divider by 2 for less jitter contribution 3 V, 1.8 V single supplies Flexible input voltage range: 1 V to 2 V (peak-to-peak) Two configurable serial outputs INL ± 1.25 LSB; DNL ± 0.25 LSB Pin compatible with the ADC1213D series HVQFN56 package Input bandwidth, 600 MHz Power dissipation, 1270 mW SPI register programming Duty cycle stabilizer High IF capability Offset binary, two’s complement, gray code Power-down mode and Sleep mode Two JESD204A serial outputs 3. APPLICATIONS
Wireless and wired broadband communications Spectral analysis Ultrasound equipment Portable instrumentation Imaging systems Software defined radio NXP Semiconductors ADC1113D125 ADC1113D125; serial JESD204A interface 4. Ordering information Table 1. Ordering information Sampling frequency (Msps) 125 Package Name HVQFN56 DESCRIPTION
Version Type number ADC1113D125HN/C1 plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 × 8 × 0.85 mm 5.
NXP Semiconductors
